The inventive concept described herein generally relates to semiconductor memory systems and, more particularly, to a semiconductor memory system including a Reed-Solomon low density parity check decoder for correcting an error of read data when stored data is read. The inventive concept also relates a read method associated with such a system.
Semiconductor memory devices are memory devices implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GeAs), and indium phosphide (InP). Generally, semiconductor memory devices are classified as either volatile memory devices or nonvolatile memory devices depending on their ability to retain stored data in the absence of supplied power.
For a variety of reasons, errors may be included in read data of a semiconductor memory device. Error correction schemes have been studied which employ error correction codes such as a Bose-Chaudhuri-Hocquenghem (BCH) code, a low density parity check (LDPC) code, and a turbo code.
A Reed-Solomon (hereinafter referred to as “RS”) code extends to the aforementioned LDPC code to achieve an RS-LDPC code. The RS-LDPC exhibits relatively superior error correction capability because its minimum distance and girth are relatively long. In spite of superior error correction capability, however, the RS-LDPC has a highly random parity check matrix structure. Disadvantageously, the random structure of parity check matrix increases a computation amount and hardware complexity of the RS-LDPC decoder.